Vector instructions (2)

The Vector Instructions are also supporting Packed Decimal. However, not as true Vector but rather just Packed Decimal calculations in registers.
The traditional decimal instructions operate in storage areas as opposed to registers.
Packed Decimal Vector Instructions have been added to allow the quicker calculation in registers. 
You are supposed to load a packed decimal value into the Vector Register,
do your calculation(s) and then store it in storage again.

The decimal instructions calculate on the entire register.
The instructions below are an example of loading two registers with values,
then add them together, and store the result back into storage

DOUBLEWORD_ALIGNED EQU 3 WORD     EQU 2           I4       EQU B'00011111' M3       EQU B'0001'      VECTOR_RESULT DS 2D          VLEF  1,V1_FLD,3         VLEF 2,V2_FLD,3         VAP 3,1,2,I4,M3         VST 3,VECTOR_RESULT,DOUBLEWORD_ALIGNED VECTOR   DS 0D     V1_FLD   DC PL4'1' V2_FLD   DC PL4'2'

The VLEF (Vector Load Element Fullword) loads a fullword value from Vn_FLD into a Vector Register. The last operand tells which fullword in the register should be updated. In this case it the fourth and last fullword. The index is zero based, i.e. zero is the first and leftmost fullword and so on.

There are other Vector Load Element instructions. They are meant for other element sizes:

• VLEB – Byte
• VLEH – Halfword
• VLEF – Fullword
• VLEG – Doubleword

The VAP (Vector Add Packed decimal) adds the two Vector Registers together. I4 specifies the number of digits are allowed in the result. In this case I just said 32 which is the entire register. M3 sets the last bit to indicate that I want the condition code set according to the result.
The result of the program is:

VECTOR REGISTER VALUES VR0...... 00000000 00000000 00000000 00000000 VR1...... 00000000 00000000 00000000 0000001C VR2...... 00000000 00000000 00000000 0000002C VR3...... 00000000 00000000 00000000 0000003C