Vector instructions (3)

This will be the last article regarding vectors.

This article deals with string (text) search which is finding the first occurrence of an element. An element can be a byte, halfword, or fullword. The string to search is in the second operand Vector Register and the element(s) to search for is(are) in the third Vector Register. The result is an offset to the element in the searched Vector Register (second operand). If you search for multiple elements the result is the first occurrence of any of the searched elements. My example will show it. 

In my example I will use byte search which you will most likely use. 

The instruction VFAEB will search for the first occurrence of either “D” or “C” in the text string “ABCDEFGHIJKLMNOP”.

Because “C” comes before “D” in the text string the result will be 2, - the offset to “C” in the text string.

VL 1,V1_FLD,DOUBLEWORD_ALIGNED                   VL    2,V2_FLD,DOUBLEWORD_ALIGNED                   VFAEB 3,1,2,1                                       VST   3,VECTOR_RESULT,DOUBLEWORD_ALIGNED            B     RETURN                               VECTOR   DS 0D                                   V1_FLD   DC CL16'ABCDEFGHIJKLMNOP'               V2_FLD   DC CL2'DC'           DC    XL14'00'

The vectors will contain the results shown below.

VECTOR REGISTER VALUES                           VR0...... 00000000  00000000 00000000 00000000 VR1...... C1C2C3C4  C5C6C7C8 C9D1D2D3 D4D5D6D7 VR2...... C4C30000  00000000 00000000 00000000 VR3...... 00000000  00000002 00000000 00000000

Vector instructions (2)

The Vector Instructions are also supporting Packed Decimal. However, not as true Vector but rather just Packed Decimal calculations in registers.
The traditional decimal instructions operate in storage areas as opposed to registers.
Packed Decimal Vector Instructions have been added to allow the quicker calculation in registers. 
You are supposed to load a packed decimal value into the Vector Register,
do your calculation(s) and then store it in storage again.

The decimal instructions calculate on the entire register.
The instructions below are an example of loading two registers with values,
then add them together, and store the result back into storage

DOUBLEWORD_ALIGNED EQU 3 WORD     EQU 2           I4       EQU B'00011111' M3       EQU B'0001'      VECTOR_RESULT DS 2D          VLEF  1,V1_FLD,3         VLEF 2,V2_FLD,3         VAP 3,1,2,I4,M3         VST 3,VECTOR_RESULT,DOUBLEWORD_ALIGNED VECTOR   DS 0D     V1_FLD   DC PL4'1' V2_FLD   DC PL4'2'

The VLEF (Vector Load Element Fullword) loads a fullword value from Vn_FLD into a Vector Register. The last operand tells which fullword in the register should be updated. In this case it the fourth and last fullword. The index is zero based, i.e. zero is the first and leftmost fullword and so on.

There are other Vector Load Element instructions. They are meant for other element sizes:

• VLEB – Byte
• VLEH – Halfword
• VLEF – Fullword
• VLEG – Doubleword

The VAP (Vector Add Packed decimal) adds the two Vector Registers together. I4 specifies the number of digits are allowed in the result. In this case I just said 32 which is the entire register. M3 sets the last bit to indicate that I want the condition code set according to the result.
The result of the program is:

VECTOR REGISTER VALUES VR0...... 00000000 00000000 00000000 00000000 VR1...... 00000000 00000000 00000000 0000001C VR2...... 00000000 00000000 00000000 0000002C VR3...... 00000000 00000000 00000000 0000003C

Vector instructions (1)

The new System z’s have included new instructions regarding vectors. Vectors are just fields with the same definition, - like integers etc. – located in a row in a general vector register. There are special registers for vectors that contains 16 bytes. Such a vector register can contain 8 halfwords, 4 fullwords, or 2 doublewords. A Vector instruction will do the same work on all fields in the Vector Register in parallel. For example, a Vector Add (VA) will add two Vector Registers together and save the result in a third Vector register.

VA    3,1,2,WORD
Add Vector Register 1 and Vector Register 2 and save the result in Vector Register 3. The values are contained in 4 fullwords.

VECTOR REGISTER VALUES VR0......00000000 00000000 00000000 00000000  VR1......00000001 00000002 00000003 00000004 VR2......00000005 00000006 00000007 00000008  VR3......00000006 00000008 0000000A 0000000C

The machine instructions are somewhat different from instructions that we are used to. 

00002 19 WORD     EQU 2 E731 2000 20F3                94 VA 3,1,2,WORD

The first byte is always X’E7’ for Vector Instructions. The last byte in the instruction will indicate the actual Vector Instruction. In this case X’F3’ tells that it is an add instruction. The assembler instruction VA is ended with a number, here 2, that tells the instruction that the vector register storage is divided in words, 4 bytes.

The following two instructions (VL) load contents into Vector Registers 1 and 2. The VA adds them together. The last (VST) stores Vector Register 3 into storage called “VECTOR_RESULT”

00003 18 DOUBLEWORD_ALIGNED EQU 3 000028                               24 VECTOR_RESULT DS 2D 000094 E710 B08E 3006       000B0 92 VL 1,V1_FLD,DOUBLEWORD_ALIGNED 00009A E720 B09E 3006       000C0 93 VL 2,V2_FLD,DOUBLEWORD_ALIGNED  0000A0 E731 2000 20F3                94 VA 3,1,2,WORD               0000A6 E730 C028 300E       00028 95 VST 3,VECTOR_RESULT,DOUBLEWORD_ALIGNED

It will be best practice to define the alignment of storage fields when you access real storage. That will speed up execution of the instructions.

The result of the VST instruction is

E5C5C3E3 D6D940D9 C5E2E4D3 E3404040 00000006 00000008 0000000A 0000000C   *VECTOR RESULT...*

The full program looks like this:

PROGRAM EQU                              DOUBLEWORD_ALIGNED EQU 3                          WORD     EQU 2                                           PROGRAM STORAGE                                   DS      CL24                             EYECATCHER DS    CL16                             VECTOR_RESULT DS 2D                                        PROGRAM STORAGE                          PGMVEC   PROGRAM START                                     MVC   EYECATCHER,=CL16'VECTOR RESULT'             VL    1,V1_FLD,DOUBLEWORD_ALIGNED                 VL    2,V2_FLD,DOUBLEWORD_ALIGNED                 VA    3,1,2,WORD                                  VST   3,VECTOR_RESULT,DOUBLEWORD_ALIGNED          B   RETURN VECTOR   DS 0D                                 V1_FLD   DS 0D                                          DC    A(1)                                        DC    A(2)           DC    A(3)           DC    A(4)  V2_FLD   DS 0D             DC    A(5)           DC    A(6)           DC    A(7)           DC    A(8)           PROGRAM END          END         PGMVEC   BINDER               END